The present invention generally relates to an interconnection for use with semiconductor devices and, in particular, relates to one such interconnection for use directly between a semiconductor device and an external connector.
Currently, most semicoductor devices, particularly those having multifunctional chips or multiple functions within a single chip are bonded into packages by the use of an intermediate member generally referred to as a header. The packages usually include pins or wires adapted to be plugged into or otherwise connected to corresponding sockets. Such an arrangement thus requires two levels of interconnection. The first level of interconnection being between the semiconductor chip and the header and the second level being between the header and the package. Such bilevel interconnections introduce considerable constraints on the manufacturing of such semiconductor devices. For example, both levels of interconnection must be tested to ensure the absence of a failure. Further, failures originating from either level increase the number of overall device failures. Still further, the pattern of either level of interconnections can constrict the freedom of design at the other levels.
A further constraint introduced by such bilevel connections is that the overall cost of such devices is continually increasing due, not only to the cost of the metals, and other materials, involved, but the increased costs of labor involved in both manufacturing the package and header and asesmbling the device.
Consequently, an interconnection that is adapted for direct connections between a wafer and an external connector can result in both a reduction in cost and a completed device having improved reliability.